Memory Bandwidth and Timing Article

If you’ve ever wondered what memory timings, latency, bandwidth and dividers all mean take a look at OCAddiction’s Memory Bandwidth and Timings Article:

"How is memory addressed?" is another common question. This one is quite simple. Think of a matrix, a collection of rows and columns. Each cell containing a 1 or 0 is defined by a location that is the intersection of a specific row and column, within a certain "bank". The older i845 Brookdale chipsets only had 4 banks, and could only address 2GB of memory. Newer Springdale and Canterwood chipsets are capable of addressing 8 banks, with a total of 4GB’s maximum of memory. How a bank is defined is mostly by the memory used. Most modules are "double sided", or have two banks on them. So in a Brookdale, you could only have one double sided module and two single sided modules, one/two/three/four single sided modules, or two double sided ones. With an i865/i875 based chipset, the combinations are much larger, especially relating to the use of double sided modules.

Lastly, "what do all these buzzwords mean? Latency, bandwidth? I’m so confused!". Those are bigger topics. Lets get to them, shall we?

Memory Bandwidth and Timing Article @ OCAddiction