Intel Launches Next Wave Of Multi-Core Server Platforms

Originally planned for early 2006, Intel Corporation’s first dual-core, hyper-threaded processors for servers with four or more processors started shipping today. The processors deliver record levels of performance2 and are optimal for multi-threaded applications such as database, supply chain management and financial services software.

The new processors are at the core of a record-setting four-processor server performance result2 recently published on the TPC-C benchmark*. TPC-C simulates a complete computing environment where a population of users executes transactions against a database and measures the number of complete business operations that can be performed by the server. More information can be found at www.tpc.org.

The Dual-Core Intel® Xeon® processor 7000 sequence, formerly codenamed “Paxville MP,” is shipping today with speeds up to 3.0 GHz and a 667 MHz dual, independent system bus. The new processors will fit into existing platforms using the Intel® E8500 chipset that was architected for dual-core and shipped earlier this year. In early 2006, Intel plans to ship new versions of the chipset and processorthat will support an 800 MHz dual, independent system bus.

The platform shipping today includes DDR2 Memory, PCI Express, advanced reliability features, and hardware-enabled support for Intel® Virtualization Technology.4 This new technology is designed to provide hardware support within the processor for virtualized server applications, providing enhanced functionality and workload support. Intel is working with the industry to turn on this capability via a BIOS switch in early 2006.

In October, Intel updated its Intel Xeon processor MP roadmap with the addition of a new platform in 2007, codenamed “Caneland,” that is planned to include a quad-core processor, codenamed “Tigerton,” based on Intel’s next generation micro-architecture. The Caneland platform is designed to deliver higher performance through a high-speed interconnect, an interface connecting each processor directly to the chipset. In addition, the Caneland platform is expected to implement an upcoming memory technology, called Fully-Buffered Dual In-Line Memory Module (FB-DIMM) and will include four memory interconnects that take advantage of the increased capabilities of the technology.