Memory Timings Defined

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Memory Timings Defined

Postby Nerbil » Sun Jul 13, 2003 10:21 pm

[Thanks to Dark Knite for the original post!]


Decoding Memory Timings: Example Corsair XMS2700 @ 2-3-3-6-1T
------------------------------------------------------------------------------
CAS Latency: 2
RAS Precharge (tRP): 3
RAS-to-CAS Delay (tRCD): 3
Bank cycle time (or tRAS): 6
Command Rate: 1T

CAS:
CAS latency is basically the number of clock cycles (or Ticks, denoted with T) between the receipt of a "read" command and when the ram chip actually starts reading. Obviously, lower numbers will result in less of a delay when memory is being read from. Corsair's website claims a low single digit % gain from CAS-3 to CAS-2. Memory can be basically visualized as a table of cell locations, and the CAS delay is invoked every time the column changes (which is far more often than the row changing). The differences in memory bandwidth concerning CAS latency were non-existent (and it is just as likely that any recorded performance gains are attributed to random events, as performance gains were not at all consistent). There was no significant gain in memory bandwidth from adjusting CAS latencies.

Precharge to Active (tRP):
The Precharge to Active timing controls the length of the delay between the precharge and activation commands. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested. The gain from optimizing the tRP value (3T to 2T) seemed to scale with higher FSBs (10MB/sec at 100 FSB, 20MB/sec at 166 FSB), giving a consistent .1% increase in performance. I highly doubt that this .1% in memory bandwidth would translate to a noticeable (or significant) real world increase.

Active to CMD (Trcd):
This timing controls the length of the delay between when a memory bank is activated to when a read/write command is sent to that bank. This basically comes into play when the memory locations are not accessed in a linear fashion (because in a linear fashion, the current bank is already activated). This option gave a consistent 20-30 MB/sec gain in memory bandwidth (3T to 2T), with the results pointing to a slight scaling at lower CAS latencies and higher FSBs.

Active to Precharge (tRAS):
The Active to Precharge timing controls the length of the delay between the activation and precharge commands -- basically how long after activation can the access cycle be started again. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested. As with CAS, the performance gain (7T to 6T) was inconsistent, and possibly could be attributed to random variables.

DRAM Command Rate (self-abbreviated DRC):
I'm going to take a quote from Adrian's Rojak Pot in order to explain this setting: "This BIOS feature controls how long the memory controller latches on and asserts the command bus. The lower the value, the faster the the memory controller can send commands out." A faster DRAM Command Rate (3T to 2T) results in a consistent 30MB/sec gain in memory bandwidth.
Last edited by Nerbil on Sun Jul 27, 2003 4:22 am, edited 2 times in total.
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Re: Memory Timings Defined

Postby Jimbob0i0 » Sun Jul 13, 2003 10:46 pm

This has been added to the tutorial thread/sticky on this board.
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Re: Memory Timings Defined

Postby RocketMBA » Sun Jul 13, 2003 11:17 pm

Superb work.
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Re: Memory Timings Defined

Postby Assimilator1 » Sun Nov 14, 2004 2:37 am

The differences in memory bandwidth concerning CAS latency were non-existent (and it is just as likely that any recorded performance gains are attributed to random events, as performance gains were not at all consistent). There was no significant gain in memory bandwidth from adjusting CAS latencies.

This just isn't true! :roll: ,whether you use SETI or Q3 as a benchmark ,going from CAS3 to CAS2 gives approximatley a 5% boost in performance (as long as the vid card is not the bottleneck) ,this is repeatable & consistent & is typical of any program that heavily uses the memory.

I don't know about the rest but as far as Active to Precharge (tRAS) goes there's something else going on here ,I'd heard that going from 5 or 6 to 10 or 11 gives a performance boost :? ,though I've forgotten the explantion for it I gave it a try this afternoon (been meaning to for over a year! :oops: ) my Q3 scores increased consistently from 250 fps to 258fps ,thats's a 3% boost for nothing :) .I've yet to see its effect on SETI.

Interesting read anyway :)
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Re: Memory Timings Defined

Postby RedDwarf » Sun Nov 14, 2004 3:40 am

Nerbil wrote:A faster DRAM Command Rate (3T to 2T)


Needs altering as it is incorrect, command rate is measured in 1 and 2T. It was correct at the top but mistyped? at the bottom.

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